Integrated high-voltage bipolar power transistor and low voltage MOS power transistor structure in the emitter switching configuration and relative manufacturing process

ABSTRACT

A description is given of two versions of an integrated structure in the emitter switching configuration comprising a high-voltage bipolar power transistor and a low-voltage MOS power transistor. In the vertical MOS version, the emitter region of the bipolar transistor is completely buried, partly in a first N- epitaxial layer and partly in a second N- epitaxial layer; the MOS is located above the emitter region. The bipolar is thus a completely buried active structure. In the horizontal MOS version, in a N- epitaxial layer there are two P+ regions, the first, which constitutes the base of the bipolar transistor, receives the N+ emitter region of the same transistor; the second receives two N+ regions which constitute the MOS source and drain regions, respectively; the front of the chip is provided with metal plating to ensure the connection between the MOS drain and the bipolar emitter contacts.

This is a divisional of co-pending application Ser. No. 07/288,405 filedon Dec. 21, 1988, now U.S. Pat. No. 5,065,213.

FIELD OF THE INVENTION

This invention relates to an integrated high-voltage bipolar powertransistor and low-voltage MOS power transistor structure in an emitterswitching configuration and to a manufacturing process therefore.

BACKGROUND OF THE INVENTION

Emitter switching is a circuit configuration in which a low-voltagepower transistor (typically an MOS transistor) cuts off the emittercurrent of a high-voltage power transistor (typically a bipolartransistor) in order to switch it off. This configuration, which upuntil now was obtained by means of discrete components, offers thefollowing advantages:

it increases the strength of bipolar transistor as far as thepossibility of inverted secondary ruptures (ESB) occurring areconcerned;

it combines the current and voltage carrying capacity of a pilotedtransistor and the high speed of a low-voltage transistor;

it enables the system to be piloted directly with linear logic circuits,through the MOS gate.

OBJECT OF THE INVENTION

In view of the advantages that an integrated circuit generally offers,as compared to an analog circuit obtained by means of discretecomponents, the object of this invention is to provide a high-voltagebipolar power transistor and a low-voltage MOS power transistor,connected together in the emitter switching configuration, andintegrated in a single chip of semiconductor material.

SUMMARY OF THE INVENTION

The integrated high-voltage bipolar power transistor and verticallow-voltage MOS power transistor structure, in the emitter switchingconfiguration of the invention comprises:

an N+ type semiconductor substrate,

an overlying semiconductor layer,

a first P type region buried in the aforesaid layer,

a second P type region connecting the first aforesaid region on thesurface, the first and second region constituting the base region of thebipolar transistor, and

a third N+ type region adjoining the aforesaid first region from belowand constituting the emitter region of the bipolar transistor.

According to the invention, the semiconductor layer consists of a firstN-type epitaxial layer and a second N-type epitaxial layer grown on it,the first region is located in the first epitaxial layer, in thevicintity of the surface adjacent to the second epitaxial layer, and thesecond region is located in the second epitaxial layer. The third regioncan consist of a completely buried layer located astride between theboundary of the first and second epitaxial layer, the body and sourceregions of the MOS can be located in the second epitaxial layer, in thevicinity of its surface and above the third region. The drain region ofthe MOS consists substantially of the region between the third regionand the aforesaid body regions. Alternatively an integrated high-voltagebipolar power transistor and horizontal low-voltage MOS power transistorstructure, in the emitter switching configuration comprises:

an N+ type semiconductor substrate,

an N- type epitaxial layer grown on the substrate,

a first P+ type region, constituting the base of the bipolar transistor,located in the layer in the vicinity of its surface, and

a second N+ type region, constituting the emitter of the bipolartransistor, adjoining the aforesaid first region from below and from theside and adjoining the surface of the layer from above. According to theinvention in the N- type epitaxial layer and in the vicinity of itssurface there is a third P+ conductivity region as well as a fourth anda fifth N+ type region. These latter regions constutute the MOS sourceand gate regions respectively and being adjacent from below and from theside to the aforesaid third region. The metal coatings of the MOStransistor drain and of the bipolar transistor emitter areinterconnected by means of tracks of conductor material.

A process for manufacturing an integrated high-voltage bipolar powertransistor and vertical low-voltage MOS power transistor structure, inthe emitter switching configuration is characterized by the fact that:

a second N conductivity epitaxial layer, designed to constitute thedrain region of the MOS transistor and at the same time automaticallyform the connection between the drain of the MOS transistor and theemitter of the bipolar transistor, is grown on the first epitaxiallayer,

the body, the source and the gate of the MOS transistor are then createdin the second epitaxial layer, by means of the known processes, incorrespondence with the aforesaid buried emitter zone of the bipolartransistor, and

a P+ type region, which enables the base region of the bipolartransistor to be electrically connected on the surface, is also createdat the side of said MOS transistor, by means of the known techniques ofoxidation, photomasking, implantation and diffusion.

Alternatively, the process is characterized in that:

a second P+ type region, separated from the first by a region of theepitaxial layer, is created in the epitaxial layer simultaneously tosaid first region,

a fourth and a fifth N+ type region, designed to constitute the MOSsource and drain region respectively, are created within the secondregion, and

the deposition of tracks of conductor material designed to electricallyinterconnect the emitter and drain metal coatings is carried outsimultaneously to the deposition of the films of conductor materialdesigned to form the gate terminals and the metal coating which ensurethe ohmic contact with the MOS source and drain regions and with thebase and emitter regions of the bipolar transistor.

BRIEF DESCRIPTION OF THE DRAWING

The above and other objects, features and advantages of our inventionwill become more readily apparent from the following description,reference being made to the accompanying highly diagrammatic drawing inwhich:

FIG. 1 is a circuit diagram which shows the equivalent electricalcircuit of the 4-terminals integrated structures, which the inventionintends to realize;

FIGS. 2-7 are diagrammatic sections which show a structure according tothe invention, in the vertical MOS power transistor version, during thevarious stages of the manufacturing process;

FIG. 8 is a section which shows the structure obtained at the end of theprocess referred to in the previous FIGS. 2-7;

FIG. 9 is a diagram of the concentrations of the various types of dopingagent along a section of the structure of FIG. 7;

FIGS. 10-11 are sections which show a structure according to theinvention, in the horizontal MOS power transistor version, during thevarious stages of the manfacturing process; and

FIG. 12 is a section which shows a schematic representation of thestructure obtained at the end of the process referred to in FIGS. 10-11.

SPECIFIC DESCRIPTION

FIG. 1 shows the equivalent electrical circuit of the 4-terminalintegrated structures that the invention intends to provide.

This circuit consists of a high-voltage bipolar power transistor Tconnected by means of its emitter to the drain of a low-voltage MOSpower transistor P.

The various stages of the manufacturing process of the integratedstructure, in the vertical MOS version, are described hereunder.

A first high resistivity N- conductivity epitaxial layer 2 is grown onan N+ type substrate 1 (FIG. 2). A P+ type region 3 is then obtained, bydeposition or implantation and subsequent diffusion, on said layer 2(FIG. 3). An N+ type region 4 is then obtained by means of the sameprocess (FIG. 4). This is followed by the growth of a second N typeepitaxial layer 5 (FIG. 5) and, by the known procedures of oxidation,photomasking, implantation and diffusion, the creation of the P+ typeregions 8, which enable the region 3 constituting the base of thebipolar transistor to be connected on the surface (FIG. 6). Alow-voltage vertical MOS power transistor and in particular the relativeP conductivity body regions 6, N+ type source regions 7 (FIG. 7), thegate 9 and the metal coatings 10, 11 and 14 for ensuring the ohmiccontact with the regions 6, 7, 8 and the substrate 1 (FIG. 8) are thencreated in the area between the two regions 8, according to knownprocedures.

FIG. 8 shows the final structure, as it appears after addition of theterminals C (collector). B (base), S (source) and G (gate) and theinsulating layer 12 of the gate 9 (said gate being connected to therelative terminal by means of the insulated conductor 13). Regions 1, 2,3 and 4 of the figure constitute, respectively, the collector, the baseand the emitter of a bipolar transistor, while region 5 constitutes thedrain of the MOS. Said drain is consequently connected directly to theemitter of the bipolar transistor thus forming a structure having as itsequivalent circuit the circuit of FIG. 1.

The emitter 4 represents a completely buried N+ type active region; bygrowing a second N type epitaxial layer 5 it is thus possible to connectthe drain of the MOS to the emitter 4 of the bipolar transistor,

The profile of the concentration (Co) of the various types of dopingagent in the different regions of the structure, along section A--A ofFIG. 7, is shown in FIG. 9, where axis x refers to the distance from theupper surface of the structure.

The manufacturing process of the integrated structure, in the horizontalMOS power transistor version, includes the following stages.

A high resistivity N- type epitaxial layer 22, which is designed toconstitute the collector of the bipolar transistor, is grown on a N+type substrate 21 (FIG. 10). Two P+ type regions 23 and 24 are thencreated simultaneously on said layer, by the known processes ofdeposition or implantation and subsequent diffusion, the first of whichbeing destined to act as a base for the bipolar transistor and thesecond to receive the MOS.

By means of the known processes of oxidation, photomasking, depositionor implantation and subsequent diffusion, an N+ type region 25 which isdestined to act as the emitter of the bipolar transistor is createdwithin the region 23, while two N+ type regions 26 and 27 which aredestined to act as the source and the drain of the MOS are createdwithin the region 24 (FIG. 11). This is followed by the formation of theMOS gate 28, the gate insulating layer 29, the metal coatings 30, 31,32, 33 and 34, which are designed to ensure the ohmic contact with theunderlying regions, and lastly the connections to the terminals S, G, Band C (FIG. 12).

The aforesaid metal coatings also include the formation of a track 35for connecting the drain D to the emitter E, so as to achieve theconnection of the two transistors in the configuration of FIG. 1.

In both the vertical MOS and horizontal versions, the final structureobtained is provided with 4 terminals, 3 of said terminals being locatedon one face of the chip and the 4th on the other face.

The described process can obviously be used to simultaneously obtain, onthe same chip, several pairs of bipolar and MOS transistors having acollector terminal in common and their base contacts, sources and gatesconnected to three respective common terminals by means of a metalcoating carried out on the front of the chip at the end of the process.

We claim:
 1. Process for manufacturing an integrated .Iadd.structurecomprising a .Iaddend.high-voltage bipolar power transistor and .Iadd.a.Iaddend.vertical low-voltage MOS power transistor . .structure.!., in ..the.!. .Iadd.an .Iaddend.emitter switching configuration, . .of thetype in which: a.!. .Iadd.having an N- type .Iaddend.first . .highresistivity N- type.!. epitaxial layer, designed to form . .the.!..Iadd.a .Iaddend.collector of . .the.!. .Iadd.said .Iaddend.bipolar.Iadd.power .Iaddend.transistor, . .is.!. grown on . .a.!. .Iadd.an.Iaddend.N+ type substrate, a P+ conductivity region, designed to serveas . .the.!. .Iadd.a .Iaddend.base of . .the.!. .Iadd.said.Iaddend.bipolar .Iadd.power .Iaddend.transistor, and . .then.!. an N+type region, designed to serve as . .the.!. .Iadd.a .Iaddend.buriedemitter . .zone.!. of . .the same.!. .Iadd.said bipolar power.Iaddend.transistor, . .are subsequently.!. created on said first.Iadd.epitaxial .Iaddend.layer, by deposition or . .implanation.!..Iadd.implantation .Iaddend.and . .subsequent.!. diffusion,..characterized by the fact that.!. .Iadd.said processcomprising.Iaddend.: a second N conductivity epitaxial layer, designedto constitute . .the.!. .Iadd.a .Iaddend.drain . .region.!. of . .the.!..Iadd.said .Iaddend.MOS .Iadd.power .Iaddend.transistor and . .at thesame time automaticaly.!. .Iadd.automatically .Iaddend.form . .the.!..Iadd.a .Iaddend.connection between . .the.!. .Iadd.said .Iaddend.drainof . .the.!. .Iadd.said .Iaddend.MOS .Iadd.power .Iaddend.transistor and. .the.!. .Iadd.said buried .Iaddend.emitter of . .the.!. .Iadd.said.Iaddend.bipolar .Iadd.power .Iaddend.transistor, is grown on . .the.!..Iadd.said .Iaddend.first epitaxial layer, . .the.!. .Iadd.a.Iaddend.body, . .the.!. .Iadd.a .Iaddend.source and . .the.!. .Iadd.a.Iaddend.gate of . .the.!. .Iadd.said .Iaddend.MOS .Iadd.power.Iaddend.transistor are . .then.!. created in . .the.!. .Iadd.said.Iaddend.second epitaxial layer, in correspondence with . .theaforesaid.!. .Iadd.said .Iaddend.buried emitter . .zone.!. of . .the.!..Iadd.said .Iaddend.bipolar .Iadd.power .Iaddend.transistor, a P+ typeregion, which enables . .the.!. .Iadd.electrical connection to be madeto said .Iaddend.base . .region.!. of . .the.!. .Iadd.said.Iaddend.bipolar .Iadd.power .Iaddend.transistor . .to be electricallyconnected on the surface.!., is . .also.!. created at the side of ..the.!. said MOS .Iadd.power .Iaddend.transistor.
 2. Process formanufacturing an integrated .Iadd.structure comprising a.Iaddend.high-voltage bipolar power transistor and .Iadd.a.Iaddend.horizontal low-voltage MOS power transistor . .structure.!., in. .the.!. .Iadd.an .Iaddend.emitter switching configuration, . .of thetype in which: a high resistivity.!. .Iadd.having an .Iaddend.N- typeepitaxial layer, designed to form . .the.!. .Iadd.a .Iaddend.collectorof . .the.!. .Iadd.said .Iaddend.bipolar .Iadd.power.Iaddend.transistor, . .is.!. grown on an N+ type substrate, a first P+type region . .is then created.!. in said epitaxial layer, a third N+type region, designed to constitute . .the.!. .Iadd.an .Iaddend.emitter. .region.!. of . .the same.!. .Iadd.said bipolar power.Iaddend.transistor, . .is then created.!. .Iadd.and .Iaddend.within ..the aforesaid.!. .Iadd.said .Iaddend.first .Iadd.P+ type.Iaddend.region, .Iadd.said first P+ type region being .Iaddend.designedto constitute . .the.!. .Iadd.a .Iaddend.base of . .the.!. .Iadd.said.Iaddend.bipolar .Iadd.power .Iaddend.transistor,.Iadd.said processbeing .Iaddend.characterized by the fact that: a second P+ type region,separated from . .the.!. .Iadd.said .Iaddend.first .Iadd.P+ type region.Iaddend.by a region of . .the.!. .Iadd.said .Iaddend.epitaxial layer,is created in . .the.!. .Iadd.said .Iaddend.epitaxial layersimultaneously . .to.!. .Iadd.with .Iaddend.said first region, a fourth.Iadd.N+ type region .Iaddend.and a fifth N+ type region, designed toconstitute . .the MOS.!. .Iadd.a .Iaddend.source and .Iadd.a.Iaddend.drain . .region.!. respectively .Iadd.of said MOS powertransistor.Iaddend., are created within . .the.!. .Iadd.said.Iaddend.second .Iadd.P+ type .Iaddend.region, the deposition of tracksof conductor material designed to electrically interconnect . .the.!..Iadd.said .Iaddend.emitter and .Iadd.said .Iaddend.drain . .metalcoatings.!. .Iadd.to each other .Iaddend.is carried out simultaneously ..to.!. .Iadd.with .Iaddend.the deposition of . .the.!. films ofconductor material designed to form . .the.!. gate terminals and . .themeatal.!. .Iadd.metal .Iaddend.coatings which ensure the ohmic contactwith . .the MOS.!. .Iadd.said .Iaddend.source and .Iadd.said.Iaddend.drain . .regions.!. .Iadd.of said MOS power transistor.Iaddend.and with . .the.!. .Iadd.said .Iaddend.base and emitter ..regions.!. of . .the.!. .Iadd.said .Iaddend.bipolar .Iadd.power.Iaddend.transistor.Iadd.; wherein said MOS power transistorcontrollably cuts off current to said emitter of said bipolar powertransistor, to provide high-voltage switching in a switched-emitterconfiguration having a primary current path between said fourth N+ typeregion and said N+ type substrate.Iaddend.. .Iadd.3. The method of claim1, wherein said body of said MOS power transistor is formed before saidsource of said MOS power transistor. .Iaddend..Iadd.4. The method ofclaim 1, wherein said body and said source of said MOS power transistorare both formed by implantation. .Iaddend..Iadd.5. A process formanufacturing an integrated high-voltage bipolar power transistor and avertical low-voltage MOS power transistor structure, comprising thesteps of: a) growing an N- type first epitaxial layer on an N+ typesubstrate, said first epitaxial layer providing a collector of saidbipolar power transistor; b) creating on said first epitaxial layer a P+conductivity region providing a base of said bipolar power transistor,and an N+ the region providing a buried emitter zone, by deposition orimplantation and diffusion; c) growing an N conductivity secondepitaxial layer on said first epitaxial layer, and forming a body regiontherein; d) creating, at an upper surface of said second epitaxiallayer, a source region and a gate of said MOS power transistorstructure, in vertical correspondence with said buried emitter zone ofsaid bipolar power transistor, e) creating a P+ type region at the sideof said MOS power transistor structure, which enables said base of saidbipolar power transistor to be electrically connected on said uppersurface. .Iaddend..Iadd.6. The method of claim 5, wherein said secondepitaxial layer is grown directly on said first epitaxial layer..Iaddend..Iadd.7. The method of claim 5, wherein said base is formedbefore said buried emitter zone. .Iaddend..Iadd.8. The method of claim5, wherein said body region is formed before said source..Iaddend..Iadd.9. The method of claim 5, wherein said body region andsaid source region are both formed by implantation. .Iaddend..Iadd.10.The method of claim 5, wherein said gate is insulated on the undersidethereof. .Iaddend..Iadd.11. A process for manufacturing a structurehaving an integrated high-voltage bipolar power transistor andhorizontal low-voltage MOS power transistor in an emitter switchingconfiguration said process comprising the steps of:growing an N- typeepitaxial layer, designed to form a collector of said bipolar powertransistor, on an N+ type substrate, creating in said epitaxial layer, afirst P+ type region, to constitute a base of said bipolar powertransistor, and a second P+ type region separated from said first P+type region by a region of said epitaxial layer; creating a third N+type region, to constitute an emitter region of said bipolar powertransistor, within said first P+ type region; creating a fourth and afifth N+ type region, to constitute a source region and a drain regionrespectively, of said MOS power transistor within said second P+ typeregion, forming a thin film of conductor material which is positionedand operatively connected to provide a field-effect-transistor-gatewhich controls conduction between said source region and said drainregion of said MOS power transistor, and forming a strip of thin filmconductor material which is positioned and operatively connected toelectrically interconnect said emitter region of said bipolar powertransistor and said drain region of said MOS power transistor; whereinsaid MOS power transistor controllably cuts off current to said emitterof said bipolar power transistor, to provide high-voltage switching in aswitched-emitter configuration having a primary current path betweensaid source region of said MOS power transistor and said collector ofsaid bipolar power transistor. .Iaddend..Iadd.12. The method of claim11, wherein said field-effect-transistor-gate is insulated on theunderside thereof. .Iaddend..Iadd.13. A process for manufacturing amicroelectronic structure which includes a vertical high-voltage bipolarpower transistor, and which also includes a vertical low-voltage MOSpower transistor structure extending to a front surface thereof,comprising the steps of:a) on an N+ type substrate, growing an N- typefirst epitaxial layer, to provide the collector of the bipolar powertransistor; b) creating, near the front surface of said first epitaxiallayer, a P+ region to provide a base of said bipolar power transistor,and an N+ type region, which is shallower than said P+ region, toprovide an emitter of said bipolar power transistor; c) growing an N+type additional epitaxial layer above said first epitaxial layer; d)forming, in said additional epitaxial layer, a P- type body region, andan N- type source region which is shallower than said body region, and aP+ sinker region which provides ohmic contact to said base; and e)creating, atop said additional epitaxial layer, an insulated gateelectrode which is capacitively coupled to at least some potions of saidbody which are laterally adjacent to said source region..Iaddend..Iadd.14. The method of claim 13, wherein said additionalepitaxial layer is grown directly on said first epitaxial layer..Iaddend..Iadd.15. The method of claim 13, wherein said base is formedbefore said emitter. .Iaddend..Iadd.16. The method of claim 13, whereinsaid body region is formed before said source region. .Iaddend..Iadd.17.The method of claim 13, wherein said body and source regions are bothformed by implantation. .Iaddend..Iadd.18. The method of claim 13,wherein said gate electrode is insulated on the underside thereof..Iaddend..Iadd.19. A process for manufacturing a solid-state structurewhich includes an integrated high-voltage bipolar power transistor, andwhich also includes a vertical low-voltage MOS power transistor,comprising the steps of:a) providing a monolithic semiconductorstructure which includes a first region which is doped with a dopant ofa first conductivity type and a second region of said first conductivitytype and is more lightly doped than said first region, and providing ametallic backside contact to said first region; b) creating, in an uppersurface of said monolithic semiconductor structure, a third region whichis doped with a second conductivity type that is opposite to said firstconductivity type, and a fourth region which is doped with said firstconductivity type; c) epitaxially growing an additional layer ofsemiconductor material of said first conductivity type above saidmonolithic semiconductor structure; d) forming, in proximity to saidfront surface,a body diffusion of said second conductivity type, and asource diffusion of said first conductivity type that is completelyseparated by said body diffusion from other portions of said additionallayer of semiconductor material, and a diffusion region of said secondconductivity type which extends upward from said third region; e)creating, atop said additional layer of semiconductor material, aninsulated gate electrode which is capacitively coupled to portions ofsaid body diffusion which are laterally adjacent to said sourcediffusion. .Iaddend..Iadd.20. The method of claim 19, wherein said bodydiffusion is formed before said source diffusion. .Iaddend..Iadd.21. Themethod of claim 19, wherein said body and source diffusions are bothformed by implantation. .Iaddend..Iadd.22. The method of claim 19,wherein said gate electrode is insulated on the underside thereof..Iaddend..Iadd.23. The method of claim 19, wherein said additional layeris grown directly on said monolithic semiconductor structure..Iaddend..Iadd.24. The method of claim 19, wherein said first region ofsaid monolithic semiconductor structure is a substrate, and said secondregion is an epitaxial layer grown on said substrate. .Iaddend..Iadd.25.The method of claim 19, wherein said first conductivity type is N- type..Iaddend.